A hardware thread (e.g., an operational core within a processor) may have the capability of entering into a power optimized state, such as a low power sleep or deep sleep state. Input/Output (I/O) traffic may send an interrupt to the hardware thread, which would generally cause the thread to wake out of the low power state to service the interrupt. For example, interrupts requiring the hardware thread to wake up may come from a Platform Component Interconnect (PCI)-Express device, a PCI device, or an input/output advanced programmable interrupt controller (IOAPIC) among others. When these interrupts arrive frequently and each of them requires the hardware thread to wake up, the purpose of putting the hardware thread into a power optimized state is defeated.